We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 7548

XPLA Professional: Designing into a CoolRunner device using VHDL or Verilog?


Keywords: XPLA, Professional, CoolRunner, fitter, VHDL, Verilog

Urgency: Standard

General Description: How do I target a CoolRunner
CPLD using VHDL/Verilog?


CoolRunner CPLDs are supported by Xilinx Synthesis Technology
(XST). XST synthesizes VHDL and Verilog designs and produces an
EDIF file of the design. The EDIF file output from XST can be imported
into XPLA Professional for compilation and fitting into a CoolRunner
CPLD. XST is available free-of-charge as part of WebPACK from
http://www.coolpld.com/products/software/webpowered.htm. An
applications note will be available soon that provides step-by-step
instructions for using XST to target a CoolRunner CPLD.

XPLA Professional currently supports Verilog design entry.
When the integration of the Coolrunner into Xilinx WebPACK
is complete, the XPLA Professional design entry support
will no longer be available.

VHDL files are not supported as a project source file in XPLA
Professional. Again, customers are encouraged to synthesis
Verilog designs with XST.

For those customers that have synthesis tools from Synplicity,
Exemplar, Synopsys, or Viewlogic, XPLA Professional supports EDIF
flows from these vendors.
AR# 7548
日期 10/31/2001
状态 Archive
Type 综合文章