AR# 75490

Vivado 2020.1.1 - GTYCHK-1 and GTYCHK-2 DRC Violations

描述

When using Vivado 2020.1.1 and a design with GTY Transceivers, I see one of the two following DRC errors:

DRC GTYCHK-1 is triggered when a VU23P - vsva1365 package combination, with all speedgrades, is used and the line rate exceeds 25.0 Gbps. The DRC can be downgraded to a warning for line rate up to 25.784Gbps. This applies only to the use of MGT Bank 231.

[DRC GTYCHK-1] GT fails Device Line Rate check: The GTYE4_CHANNEL cell DUT/inst/cmac_usplus_0_gt_i
/inst/gen_gtwizard_gtye4_top.cmac_usplus_0_gt_gtwizard_gtye4_inst
/gen_gtwizard_gtye4.gen_channel_container[7].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst
/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST in site GTYE4_CHANNEL_X0Y28 is limited to a total GT Line Rate of 25.00 Gbps. The Line Rate for that GT is calculated to be 25.78, which exceeds the supported limit. Please check your design.

DRC GTYCHK-2 is triggered when a VU23P - vsva1365 package combination, with all speedgrades, is used and the line rate exceeds 16.0 Gbps when using any bank except MGT Bank 231.
For PCIe Gen4 (16.0 Gbps) designs, the tool reports the following DRC error:

[DRC GTYCHK-2] GT fails Bank Line Rate check: The GTYE4_CHANNEL cell pcie4c_uscale_plus_0_i/inst/gt_top_i
/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/pcie4c_uscale_plus_0_gt_i
/inst/gen_gtwizard_gtye4_top.pcie4c_uscale_plus_0_gt_gtwizard_gtye4_inst
/gen_gtwizard_gtye4.gen_channel_container[3].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst
/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST in site GTYE4_CHANNEL_X0Y14 is limited to a total GT Line Rate of 16.00 Gbps. The Line Rate for that GT is calculated to be 20.00, which exceeds the supported limit for the associated Bank 227. This Line Rate could be supported by the GTs associated with Bank 231. Please adjust your design as appropriate.



解决方案

The calculation is done incorrectly to 20.0 Gbps. There is no functional issue so it can be ignored.

The DRC can be downgraded to a warning for PCIe Gen4 designs as described below.

This issue will be resolved in an upcoming release of Vivado. When using Vivado 2020.1.1, please use one of the following methods to work around the issue.

Work-around 1:

Downgrade the DRCs to warnings using the following commands at run time

set_property SEVERITY {Warning} [get_drc_checks GTYCHK-1]
set_property SEVERITY {Warning} [get_drc_checks GTYCHK-2]

Work-around 2:

Use the waiver mechanism to disable each violation. After the DRC is reported, select the GTYCHK-1 or GTYCHK-2 DRC violations, right-click, and select "create waiver".

The following syntax will do the same.

See the "Creating a Waiver" section of (UG906) for more information.

create_waiver -of_objects [get_drc_violations -name drc {GTYCHK-1#1}] -user <user> -description AR_75490_waiver
create_waiver -of_objects [get_drc_violations -name drc {GTYCHK-2#1}] -user <user> -description AR_75490_waiver

 

AR# 75490
日期 08/20/2020
状态 Active
Type 综合文章
Tools
IP