Configurations of the FIR compiler will fail in compilation if the configuration calls for a coefficient width of greater than 48 bits.
The error will be similar to the following:
ERROR: [VRFC 10-1121] no index value can belong to null index range [/wrk/HEAD/continuous/2019_08_03_2609561/packages/customer/vivado/data/ip/xilinx/fir_compiler_v7_2/hdl/fir_compiler_v7_2_vh_rfs.vhd:5018]
ERROR: [XSIM 43-3321] Static elaboration of top level VHDL design unit testfir_tb in library work failed.
To resolve this issue, split the FIR into multiple identical FIRs with the same configuration apart from coefficient width, with coefficients spliced into an upper signed splice and one or more unsigned lesser significant splices.
Feed the sample data into all in parallel. On output, shift the outputs according to the weight of the coefficient splices, then add the resulting partial products.
For an original width of 49 bits:
Split it into 2 FIRs of 25 bits signed and 24 bit unsigned (25 bits signed, but zero padded).
Shift the output of the first FIR up by 24 bits before adding.