We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!


AR# 7579

XPLA Programmer - XPLA1 ISP Proto Board CPLD does not function properly.


Keywords: XPLA, PC-ISP, programmer, ISP, ISC, JTAG, CoolRunner,
demo, board, proto, CPLD, XPLA1, XCR5128, pz3128, XCR3128,

Urgency: Standard

General Description:
Why does the XPLA1 ISP Demo Board CPLD function improperly?


The on-board clock circuit on the ISP demo board produces a clock
with rise and fall times that are slower than those specified in the data sheet.
This can cause improper clocking within the part, causing unpredictable

The slow rise/fall time is due to a termination resistor on the board, R2,
which provides termination if an external clock is used for the board.
This resistor should be removed from the board if the on-board clock
circuit is being used.
AR# 7579
日期 08/31/2001
状态 Archive
Type 综合文章