When a MIPI D-PHY TX IP core for Versal devices is generated with Vivado 2020.3 or earlier versions, it can have rising edge misalignment between clock and data outputs.
How can I work around this?
This is a known limitation for the MIPI D-PHY TX IP when generated with Vivado 2020.3 or earlier versions.
It also applies to any subsystem IP using this IP such as the MIPI CSI-2 TX Subsystem or MIPI DSI TX Subsystem.
When a Versal MIPI D-PHY TX IP is interfacing with other D-PHY RX based systems, all MIPI D-PHY RX IP cores with dual edge logic for leader sequence detection (including the Xilinx MIPI D-PHY RX) will be able to receive the MIPI D-PHY TX misaligned data correctly.
This misalignment is only observed for MIPI D-PHY RX cores that have sequence detection logic with rising edge alignment. In these cases, the issue manifests as a sequence detection failure.
To address this misalignment, an option to select MIPI D-PHY TX configuration will be added in Vivado 2021.1. This will enable alignment for MIPI D-PHY RX cores that have sequence detection logic with rising edge alignment. Please see (PG202) for details of the additional option.
This limitation is only observed in MIPI D-PHY TX IP cores for Versal devices generated with Vivado 2020.3 or earlier versions.
For a detailed list of MIPI D-PHY Release Notes and Known Issues, see (Xilinx Answer 54550)