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AR# 7595

8.2i CPLD CoolRunner-II XPLA3/XC9500 families - How do I create a delay buffer?

Description

Keywords: 8.1i, 7.1i, 6.3i, 6.2i, 6.1i, 5.2i, 5.1i, 4.1i, 4.2i, XST, 9500XL, 9500XV, line

How do I add a level of logic delay to one signal?

解决方案

1

Do not expect a level of logic delay to be the same from part to part since some devices are faster than others. Also, all CMOS devices speed up at colder temperatures and higher voltages, so you cannot assume that the delay is always constant.

You can add a level of logic delay to one signal by instantiating a BUF component, and then placing a KEEP attribute on the input so the synthesis tool and the CPLD fitter do not optimize it away (since it is redundant logic). The KEEP attributes must be set in the source code (VHDL/Verilog/Schematic) or the buffers will be removed by synthesis.

If the signal that is being delayed is a combinatoral signal, then the first buffer that is instantiated does not add any extra delay; it explicitly states the path through the macrocell that the path takes. Additional buffers will add additional delay.
2 x buffers are needed to create the equivalent of 1 delay buffer.
3 x buffers are needed to create the equivalent of 2 delay buffers, etc.


VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

library UNISIM;
use UNISIM.VComponents.all;

entity top is
Port ( din : in std_logic;
clk : in std_logic;
dout: out std_logic);
end top;

architecture behavioral of top is

signal dout_node : std_logic ;--define the output-signal of the flip-flop

attribute KEEP : string;
attribute KEEP of dout_node : signal is "TRUE"; --keep buffer from being optimized out

component buf
port( i : in std_logic; o : out std_logic);
end component;

begin

my_buf : buf
port map (
i => dout_node,
o => dout);

process (din, clk)
begin
if (clk'event) and (clk='1') then
dout_node <= din;
end if;
end process;

end behavioral;

2

Verilog

module top(input_a,clk,comb);
input input_a;
input clk;
output comb;

reg input_a_reg;

//synthesis attribute keep of input_a_reg is "true"
BUF mybuf (.I(input_a_reg),.O(comb));

always @(posedge clk)
begin
input_a_reg <= input_a;
end

endmodule

3

ABEL (Must use ABEL XST Verilog flow)

MODULE top
clk PIN;
din PIN;
dout PIN;

delay node istype 'keep';

BUF external (I -> O);
U1 functional_block BUF;

EQUATIONS

U1.I = din;
delay = U1.O;

dout := delay;
dout.clk = clk;

END

4

Schematic (XST VHDL flow)

Perform the following steps:
1. Insert a BUF component.
2. Double-click the output net to display the Object Properties box. Click "New."
3. In the Pull-down menu for Attribute Name, select "KEEP." Leave the other fields blank, and then click "OK."
4. Select the new KEEP attribute and click "Edit Traits." Under Category, select "VHDL."
5. Select the radio button for Write this Attribute (this allows you to select the check-boxes underneath). Check Item 2 (In an attribute declaration statement) and Item 3 (In an attribute statement).
6. Click "OK" to return to the Object Properties menu, and then click "OK" again to return to the schematic view.

Each BUF component forces the fitter to use an extra level of logic delay.
AR# 7595
创建日期 08/21/2007
Last Updated 07/25/2008
状态 Active
Type 综合文章