描述

When I cascade two CLKDLLs together with the Lock signal of the first CLKDLL driving the RST of the second CLKDLL, the second CLKDLL never locks, and its outputs do not have the correct clock frequencies. This issue happens on the board after the design is downloaded, and the functional/timing simulation did not exhibit this problem.

解决方案

To work around this problem, insert an SRL16 and an inverter between the LOCKED and RST pin of the first and second CLKDLL.

For more information, please see (Xilinx XAPP132): "Using the Virtex Delay-Locked Loop."