AR# 782: How can hold time violations occur when the data book states 0 ns hold times?
AR# 782
How can hold time violations occur when the data book states 0 ns hold times?
解决方案
How can hold time violations occur when the data book states 0 ns hold times?
Most simulators must simulate Xilinx CLB set-up times as hold times. The reason for this is in the point of view. The data book uses the CLB input pins as points of reference while simulators must use the actual input pins on the CLB flip-flop. An XC4005-6 CLB will be used in the following example showing how the set-up and hold time requirements of a path through a function generator input are modified depending on your point of view.
Graphically, the reference points used to calculate the data book set-up and hold time requirements are (A) and (B):
The first point (A) is any CLB function generator input pin. The second point (B) is the CLB clock pin. The data book states the following numbers for an XC4005-6 device:
Set-up time before clock at F/G inputs: 6.0 ns Hold time after clock at F/G inputs: 0.0 ns
If you were to draw the waveform of a signal tied to G4 that just meets the above set-up and hold time requirements, you would get:
+------+ point | | (A) | | +---+ +-------------------------------------------+
Because point (C) is after the function generator, we must delay the above waveform seen at point (A) by the delay through the function generator. This delay is roughly equivalent to, and in most cases exactly the same as, the F/G input to X/Y output delay. The data book states the following number for an XC4005-6 device:
F/G inputs to X/Y outputs: 6.0 ns
If we now draw the waveform that is expected at point (C) we get:
+------+ point | | (C) | | +----------+ +------------------------------------+
Notice that set-up time Ts shown at point (A) is now a hold time Th. Finally, because the clock pin might also have a delay associated with it, the clock reference may also be delayed. This will shift the clock waveform and thereby modify Ts and Th once again.
The above example shows the shift using the function generator inputs however you can apply the same concept to the other inputs pins on the CLB.