UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!
  1. Xilinx -灵活应变.万物智能.
  2. 技术支持
  3. AR# 7822: Exemplar - How do I infer an SRL16 for Virtex/-E devices in HDL (Verilog/VHDL)?

AR# 7822

Exemplar - How do I infer an SRL16 for Virtex/-E devices in HDL (Verilog/VHDL)?

描述

Keywords: SRL, inferring, 1999, 1e

Urgency: Standard

General Description:
The latest version of LeonardoSpectrum (1999.1e at the writing of this answer record) supports the inferring of SRL16s for Virtex designs. The following two variables control this:

- The first variable enables SRL mapping (default: TRUE):
set virtex_map_srl true

- The second variable packs the SRL into a single slice (default: TRUE):
set virtex_map_srl_pack true

NOTE:
- In Synplify, the SRL is mapped by default when possible.
- Synplify currently does not map to an SRL when the pipeline (cycle) is two and under. This will be fixed in the next software release.

The following coding styles work for both Exemplar and Synplify.

解决方案

1

VHDL Example Design of SRL16 Inference for Virtex

NOTE: This design infers sixteen SRL16s with a 16-pipeline delay.

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity pipeline_delay is
generic (cycle : integer := 16;
width :integer := 16);
port (input :in std_logic_vector(width - 1 downto 0);
clk :in std_logic;
output :out std_logic_vector(width - 1 downto 0));
end pipeline_delay;

architecture behav of pipeline_delay is
type my_type is array (0 to cycle -1) of std_logic_vector(width -1 downto 0);
signal int_sig :my_type;

begin

main :process (clk)
begin
if clk'event and clk = '1' then
int_sig <= input & int_sig(0 to cycle - 2);
end if;
end process main;

output <= int_sig(cycle -1);

end behav;

2

Verilog Example SRL

NOTE: This design infers three SRL16s with a 4-pipeline delay.

module srle_example (clk, enable, data_in, result);
parameter cycle=4;
parameter width = 3;

input clk, enable;
input [0:width] data_in;
output [0:width] result;

reg [0:width-1] shift [cycle-1:0];
integer i;

always @(posedge clk)
begin

if (enable == 1) begin
for (i = (cycle-1);i >0; i=i-1) shift[i] = shift[i-1];
shift[0] = data_in;
end
end
assign result = shift[cycle-1];
endmodule
AR# 7822
日期 04/24/2007
状态 Archive
Type 综合文章
的页面