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AR# 7856

Viewlogic VHDL simulation:How to simulate Xilinx Virtex primitives (e.g. ramb4_s4)

Description

Keywords: viewlogic, fusion, primitive, ram
Urgency: Normal
Problem Description:
When customer is simulating in Viewlogic, the Xilinx primitives such as ramb4_s4 will not simulate.

解决方案

For functional simulation, you want to use the UNISIM and not the SIMPRIM
library. Under vhdl\src\unisims, you want to compile the following files in order:

unisim_vpkg.vhd
unisim_vcomp.vhd
unisim_vital.vhd

This will allow to simulate instantiated components in your code like a
RAMB4_S4_S4.

For timing simulation, Xilinx distributes a VHDL library for the RAMB4_S4_S4 that you have to compile in SpeedWave before you compile the model containing the instance of the primitive. When you get into Fusion, open the Library Manager and create a library SIMPRIM. From your Xilinx install directory (xilinx), add the file xilinx\vhdl\src\simprims\simprim_Vpackage.vhd and analyze. Then, in your user library, add xilinx\vhdl\src\simprims\simprim_VITAL.vhd and analyze. Then add and analyze your file that instantiates the RAMB4_S4_S4, e.g.
AR# 7856
创建日期 09/01/2007
Last Updated 11/13/2002
状态 Archive
Type ??????