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AR# 7889

2.1i Floorplanner/Virtex - Misaligned BUFT output signals at RXXCXX

Description

Keywords: misaligned, buft, floorplanner, 2.1i, Virtex

Urgency: Standard

General Description:
After I implement a design without errors, opening the design in the Floorplanner and performing a "Check Floorplan" causes the following error message:

"Misaligned BUFT output signals at RXXCXX."

解决方案

This is caused by a problem with the Floorplanner DRC check. The warning messages are safe to ignore and will not affect operation of the tools in any other way.

This is fixed in the next software release.
AR# 7889
日期 07/09/2001
状态 Archive
Type ??????