You are using a deprecated Browser. Internet Explorer is no longer supported by Xilinx.
2.1i COREGEN, C_IP3, Distributed Memory: Customization GUI does not indicate what legal data width and depth ranges are
Keywords: ram, distributed memory, range, width, depth, virtex, spartan2
The Distributed Memory customization GUI does not indicate what legal data width and depth
The legal data width and depth values are described in the datasheet for this
module as follows:
width: 1 to 64 bits
depth: 16 to 256 in steps of 16 (16, 32, 48, 64, etc.)