We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 7973

3.1i CORE Generator, ModelSim (MTI): Warning messages are seen when compiling VHDL designs that contain COREGen modules. (VHDL)


Keywords: ModelSim, COREGen, CORE Generator, VHDL, MTI, binding, default, configuration

Urgency: Standard

General Description:
When I compile VHDL behavioral simulation netlists containing CORE Generator modules in ModelSim, warning messages such as the following appear:

# WARNING[1]: vfft64_lab.vhd(168): No default binding for component: "ram6416".
(No entity named "ram6416" was found)


When these warning are associated with CORE Generator modules, they are generally not a cause for concern if the modules have been instantiated properly. Warnings such at this will occur with all 2.1i COREGen modules, because the simulator encounters the component declaration for the CORE Generator module without first seeing an entity declaration for it.

The binding problem is resolved lower down in the design code in the VHDL configuration block, which points to the simulation model in the compiled "xilinxcorelib" library that is used to model the core.

You should verify that the reference to the core in the configuration block has been merged successfully into the design simulation; this can be done by monitoring the compile messages that follow this warning.

For example, suppose a dual-port block memory module has been instantiated in a design called "vfft64_lab"; the reference to the block memory module is specified in a VHDL configuration block called "cfg_vfft64_lab_tb" in the testbench file vfft64_lab_tb.vhd.

If the module binding has been resolved successfully, you should see something like this:

# -- Compiling configuration cfg_vfft64_lab_tb
# -- Loading entity vfft64_lab_tb
# -- Loading architecture testbench of vfft64_lab_tb
# -- Loading architecture xilinx of fft64
# -- Loading package vital_timing
# -- Loading package vcomponents
# -- Loading entity vfft64
# -- Loading package ul_utils
# -- Loading package mem_init_file_pack
# -- Loading entity c_mem_dp_block_v1_0

The lines of interest are:

1. The line indicating that the configuration is being compiled:

# -- Compiling configuration cfg_vfft64_lab_tb

2. The line indicating that the entity for the module you instantiated ("c_mem_dp_block_v1_0" in this dual-port block memory example), as well as the modules it depends upon, are being loaded:

# -- Loading package ul_utils
# -- Loading package mem_init_file_pack
# -- Loading entity c_mem_dp_block_v1_0

As long as you can verify that the necessary packages and entities required by the module have been loaded, the warning at the beginning regarding "no default binding" for this component can be safely ignored.

However, if the configuration statement is not set up correctly, or the binding is not declared, you will see a similar warning while simulation is loaded up (VSIM). If this happens, go back and check that:
1. The configuration statement is correct and is being compiled
2. The configuration statement (rather than the testbench) is being loaded in the simulator (VSIM).
AR# 7973
日期 09/05/2002
状态 Archive
Type ??????