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AR# 7994

2.1i: VHDL simulation of XDW module COMP_LT_UBIN_x gives wrong results

Description

Keywords: VHDL, simulation, XDW, Synopsys, DesignWare, Compiler

Urgency: Standard

General Description:
When doing a VHDL simulation with Alliance 2.1i of XDW modules COMP_LT_UBIN_x the
results from the compare are wrong. After the result has been '1' for the first time it stays '1'
for the rest of the simulation.

解决方案

This is due to an improper variable initialization in the XDW library. To fix this you have to manually
edit the XDW source files. Open $XILINX/synopsys/libraries/sim/xdw/src/xdw_VITAL.vhd
in an editor. The description of a comparator looks like this:


...
library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity COMP_LT_UBIN_4 is
port (
Z : out STD_ULOGIC;
A : in STD_LOGIC_VECTOR (3 downto 0);
B : in STD_LOGIC_VECTOR (3 downto 0));

end COMP_LT_UBIN_4;

architecture COMP_LT_UBIN_4_V of COMP_LT_UBIN_4 is

begin

VITALBehavior : process (A, B)

VARIABLE O_zd : STD_ULOGIC := '0';

begin
-------------------------
-- Functionality Section
-------------------------
for I in 3 downto 0 loop
if (((NOT A(I)) AND B(I)) = '1') then
O_zd := '1';
exit;
elsif ((A(I) AND (NOT B(I))) = '1') then
exit;
end if;
end loop;
Z <= O_zd after 0.1 ns;
end process;

end COMP_LT_UBIN_4_V;
...



To get a correct initialization of the variable you have to insert:

O_zd := '0',

directly after the begin of the process:


...
library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity COMP_LT_UBIN_4 is
port (
Z : out STD_ULOGIC;
A : in STD_LOGIC_VECTOR (3 downto 0);
B : in STD_LOGIC_VECTOR (3 downto 0));

end COMP_LT_UBIN_4;

architecture COMP_LT_UBIN_4_V of COMP_LT_UBIN_4 is

begin

VITALBehavior : process (A, B)

VARIABLE O_zd : STD_ULOGIC := '0';

begin

O_zd := '0', -- THIS LINE MUST BE ADDED !!!

-------------------------
-- Functionality Section
-------------------------
for I in 3 downto 0 loop
if (((NOT A(I)) AND B(I)) = '1') then
...
...


Re-analyze the library. Now you will get the correct results.

This issue has been fixed for the next version of Alliance software.
AR# 7994
创建日期 11/03/1999
Last Updated 06/13/2002
状态 Archive
Type 综合文章