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AR# 8007

Virtex CLKDLL - Why is the output jitter specification in the data sheet less than the cycle-to-cycle input jitter?


The data sheet indicates that the cycle-to-cycle input jitter is +/-300 ps, but that the output cycle-to-cycle jitter is +/-60 ps. How is it possible that the output jitter is shorter than the input jitter?


The DLL output jitter and skew specifications do not include input clock jitter. Because input clock jitter can vary considerably between applications, input jitter is not included in the DLL output specs. Consequently, the DLL output jitter spec of +/-60 ps is the amount of jitter that the DLL can add to the existing input clock jitter.

Remember that the DLL is a delay line, not a clock generator (like a PLL), so a clean input clock will lead to a clean output clock, and a flawed input clock will lead to a flawed output clock (with the exception that the input clock can be duty-cycle corrected).

The DLL output cycle-to-cycle jitter of +/-60 ps is based on CLKDLL tap adjustment. Other factors such as input jitter, internal DLL delay, and routing also contribute to the resulting cycle-to-cycle jitter. See (Xilinx Answer 13397) for more information on cycle-to-cycle jitter.

For timing budgeting, use the period jitter. See (Xilinx Answer 13645) for more information.

AR# 8007
日期 12/15/2012
状态 Active
Type 综合文章