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AR# 8020

2.1i COREGEN: Incorrect latency modelling and race condition in Verilog model for 4K Constant Coefficient Multiplier core

Description

Keywords: verilog, constant, coefficient, multiplier, latency, VCS, 1.5

Urgency: standard

General Description:
The following problems may be seen with the Verilog model for the 4K
Constant Coefficient Multiplier core shipped in the 1.5 and 2.1i releases
of the CORE Generator when simulating in Synopsys VCS or Cadence
Verilog-XL:

1. The number of latency cycles may be incorrect, usually short by 1 cycle.
2. Race condition associated with transitioning of the output on a rising clock edge

The problems are similar to those found in the Virtex Dynamic Constant Coefficient
Multiplier Verilog model as described in (Xilinx Solution #8020).

解决方案

This problem is fixed in the C_IP4 IP release, which can be downloaded from:

http://www.xilinx.com/ipcenter/coregen/updates.htm
AR# 8020
创建日期 11/08/1999
Last Updated 04/02/2002
状态 Archive
Type 综合文章