entity flops is port( di: in std_logic; ce : in std_logic; clk: in std_logic; qo: out std_logic; rst: in std_logic);
end flops;
architecture inst of flops is component FDCE port( D: in std_logic; CE: in std_logic; C: in std_logic; CLR: in std_logic; Q: out std_logic); end component;
attribute RLOC: string; attribute RLOC of U0: label is "R0C0.S0"; attribute RLOC of U1: label is "R0C1.S0"; attribute RLOC of U2: label is "R1C1.S0"; signal q0,q1 : std_logic;
begin U0 : FDCE port map(D => di, CE=> ce, C => clk, CLR => rst, Q => q0);
U1: FDCE port map(D => q0, CE=> ce, C => clk, CLR => rst, Q => q1);
U2: FDCE port map(D => q1, CE=> ce, C => clk, CLR => rst, Q => qo);
end inst;
3
VHDL LOC example -- Exemplar and Synplify --
library IEEE; use IEEE.std_logic_1164.all;
entity flops is port( di: in std_logic; ce : in std_logic; clk: in std_logic; qo: out std_logic; rst: in std_logic);
end flops;
architecture inst of flops is component FDCE port( D: in std_logic; CE: in std_logic; C: in std_logic; CLR: in std_logic; Q: out std_logic); end component;
attribute LOC: string; attribute LOC of U0: label is "CLB_R2C3.S0"; attribute LOC of U1: label is "CLB_R2C4.S0"; attribute LOC of U2: label is "CLB_R6C8.S0"; signal q0,q1 : std_logic;
begin U0 : FDCE port map(D => di, CE=> ce, C => clk, CLR => rst, Q => q0);
U1: FDCE port map(D => q0, CE=> ce, C => clk, CLR => rst, Q => q1);
U2: FDCE port map(D => q1, CE=> ce, C => clk, CLR => rst, Q => qo);
end inst;
4
Verilog LOC example using Synplify attribute
For Exemplar, replace the attribute with: examplar attribute <instance_name> loc <location>
For example: replace /*synthesis rloc="r1c0.s0" */ with /*exemplar attribute u0 rloc r1c0.s0 */ ----------------------------------------------------------------