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AR# 8074

EXEMPLAR 1999.1x - How do I configure I/O standards (IOSTANDARD attribute) on to ports using HDL attributes? (VHDL/Verilog)

Description

Keywords: PCI_33_GTL, I/O, IO standards, buffers, TCL script, LVDS, LVPECL, IOSTANDARD

Urgency: Standard

General Description:
I want to use a specific I/O standard in my design. How can I use the I/O standard buffer using an Exemplar TCL script (command line) in my HDL code?

解决方案

1

To use a TCL script for non-differential I/O standards, you need to know the top-level port name, and then you can use an attribute from the command line or from a script.

Example
The following example has a top-level port name of data_in:

set part v50ecs144

- Use "xcv" library for Virtex, and "xcve" for Virtex-E:
load_library xcve

- Read the VHDL/Verilog file:
read d_register.v

- Set the PAD attribute to the "data_in" port:
PAD IBUF_PCI_33_GTL data_in

optimize -target xcve
auto_write ff_example.edf

2

Using a VHDL attribute to configure the LVDS I/O standard
- To use LVPECL, replace "LVDS" with "LVPECL."
- To use TCL script with this example, remove the PAD attribute in the code and set it in the TCL file.

Example
The following example illustrates input, output, and bidirectional I/O:

library IEEE, exemplar;
use IEEE.std_logic_1164.all;
use exemplar.exemplar_1164.all;

entity LVDSIO_att is
port (CLK, DATA, Tin : in STD_LOGIC;
IODATA_p, IODATA_n : inout STD_LOGIC;
Q_p, Q_n : buffer STD_LOGIC
);
attribute pad: string;
attribute pad of clk : signal is "IBUFG_LVDS";
attribute pad of DATA: signal is "IBUF_LVDS";
attribute pad of Tin : signal is "IBUF_LVDS";
attribute pad of Q_p : signal is "OBUF_LVDS";
attribute pad of Q_n : signal is "OBUF_LVDS";
attribute pad of IODATA_p: signal is "IOBUF_LVDS";
attribute pad of IODATA_n: signal is "OBUFT_LVDS";
attribute buffer_sig of clk: signal is "BUFG";
end LVDSIO_att;


architecture BEHAV of LVDSIO_att is
signal iodata_in: std_logic;
signal iodata_out : std_logic;
signal iodata_n_out: std_logic;

begin
My_D_Reg: process (CLK, DATA)
begin
if (CLK'event and CLK='1') then
Q_p <= DATA;
end if;
end process; -- End My_D_Reg

Q_n <= not Q_p;
iodata_out <= DATA and iodata_in;
iodata_in <= iodata_p;
iodata_n_out <= not iodata_out;

io_p:process (Tin)
begin
if (Tin = '0') then
iodata_p <= iodata_out;
else
iodata_p <= 'Z';
end if;
end process;

io_n:process (Tin)
begin
if (Tin = '0') then
iodata_n <= iodata_n_out;
else
iodata_n <= 'Z';
end if;
end process;
end BEHAV;

3

Using a Verilog attribute to configure LVDS I/O standard
- To use LVPECL, replace "LVDS" with "LVPECL."
- To use TCL script with this example, remove the PAD attribute in the code and set it in the TCL file.

Example
The following example illustrates input, output, and bidirectional I/O:

module LVDSIO_att (CLK, DATA, Tin, IODATA_p, IODATA_n, Q_p, Q_n);
input CLK; // exemplar attribute CLK PAD IBUFG_LVDS
/* I want to add another attribute for CLK to infer BUFG */

input DATA; //exemplar attribute DATA PAD IBUF_LVDS
input Tin; // exemplar attribute Tin PAD IBUF_LVDS
inout IODATA_p; // exemplar attribute IODATA_p PAD IOBUF_LVDS
inout IODATA_n; //exemplar attribute IODATA_n PAD OBUFT_LVDS
output Q_p; //exemplar attribute Q_p PAD OBUF_LVDS
output Q_n; // exemplar attribute Q_n PAD OBUF_LVDS

wire iodata_in;
wire iodata_out;
wire iodata_n_out;
reg Q_p;

always @(posedge CLK)
begin
Q_p <= DATA;
end

assign Q_n = ~Q_p;
assign iodata_out = DATA && iodata_in;
assign iodata_in = IODATA_p;
assign iodata_n_out = ~iodata_out;

assign IODATA_p = (Tin== 1'b0)? iodata_out: 1'bZ;
assign IODATA_n = (Tin == 1'b0)? iodata_n_out: 1'bZ;

endmodule
AR# 8074
创建日期 11/16/1999
Last Updated 04/24/2007
状态 Archive
Type 综合文章