UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!
  1. Xilinx -灵活应变.万物智能.
  2. 技术支持
  3. AR# 8183: SYNPLIFY: How to infer ROM in HDL (VHDL/Verilog)?

AR# 8183

SYNPLIFY: How to infer ROM in HDL (VHDL/Verilog)?

描述

Keywords: Asynchronous, select, rom, synplicity

Urgency: Standard

General Description:
One of the new features in Synplify 5.3 is ROM inference.
Synplify 5.3 now maps these inferred ROMs to Xilinx ROM primitives, ROM16X1 and
ROM32X1.
Xilinx ROM primitives are inferred with the use of an attribute called syn_romstyle.
Currently, the only supported value for this attribute is 'select_rom'. This attribute is
set on the output of the ROM as in examples below.

Note: Tested in Synplicity 5.3.

解决方案

1

//Verilog example

module testrom(a, z);
input [3:0] a;
output [3:0] z;

reg [3:0] z /* synthesis syn_romstyle = "select_rom" */;

always @(a)
begin
case(a)
4'b0000: z = 4'hA;
4'b0001: z = 4'h4;
4'b0010: z = 4'h7;
4'b0011: z = 4'h2;
4'b0100: z = 4'h5;
4'b0101: z = 4'h9;
4'b0110: z = 4'hB;
4'b1001: z = 4'h1;
4'b1010: z = 4'hF;
4'b1011: z = 4'h6;
4'b1100: z = 4'h8;
4'b1101: z = 4'hE;
4'b1110: z = 4'hC;
default : z = 4'h0;
endcase
end

endmodule

2

-- VHDL example

library IEEE;
use IEEE.std_logic_1164.all;
entity rom is
port ( a: in std_logic_vector(3 downto 0);
z: out std_logic_vector(3 downto 0)
);
attribute syn_romstyle : string;
attribute syn_romstyle of z : signal is "select_rom";
end rom;

architecture rtl of rom is
begin
process(a)
begin
case a is
when "0000" => z <= "1010";
when "0001" => z <= "0100";
when "0010" => z <= "0111";
when "0011" => z <= "0010";
when "0100" => z <= "0101";
when "0101" => z <= "1001";
when "0110" => z <= "1011";
when "1001" => z <= "0001";
when "1010" => z <= "1111";
when "1011" => z <= "0110";
when "1100" => z <= "1000";
when "1101" => z <= "1110";
when "1110" => z <= "1100";
when others => z <= "0000";
end case;
end process;
end rtl;

3

# SDC example
In Synplify, run the vhdl/verilog design once and go to HDL Analyst -> RTL -> Hierarchical View.
Note the ROM module name, e.g.: z_18[3:0].

Click on New Constraint File Icon, select Attributes tab and enter the following:
z_18[3:0] (rom instance name) under 'Object' column
syn_romstyle under attribute column, and
select_rom under value column.

Save and rerun.

Alternatively, you can enter the following in <filename>.sdc :
define_attribute {z_18[3:0]} syn_romstyle {select_rom}
AR# 8183
日期 04/24/2007
状态 Archive
Type 综合文章
的页面