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AR# 8213

FPGA Configuration - Configuration will not begin

Description

General Description:

This Answer Record describes conditions that you should check if your FPGA is stuck in a state in which configuration has not begun. This information is valid for all Xilinx devices except for Virtex devices.

解决方案

Mode pins are set incorrectly

MODE...............................| MODE PINS |

..........................................| <M2:M1:M0> |

=======================================================

Slave Serial.......................| 111..............| XC4000, XC5200, XC3000

Master Serial.....................| 000..............| XC4000, XC5200, XC3000

Master Parallel Up.............| 100..............| XC4000, XC5200, XC3000

Master Parallel Down........| 110..............| XC4000, XC5200, XC3000

Synchronous Peripheral.....| 011.............| XC4000, XC5200

Asynchronous Peripheral...| 101.............| XC4000, XC5200, XC3000

Express..............................| 010.............| XC4000(XLA/XV only), XC5200

MODE.................................| MODE PIN |

=======================================================

Slave Serial........................|....1..............| Spartan

Master Serial......................|....0..............| Spartan

MODE................................| MODE PINS |

...........................................| <M1:M0> |

=======================================================

Slave Serial........................|.....11............| Spartan-XL

Master Serial......................|.....10............| Spartan-XL

Express..............................|.....0X............| Spartan-XL

Key:

1: Indicates a logic level High

0: Indicates a logic level Low

X: Indicates a 'don't care'

Logic Levels:

While all Xilinx devices have internal pullups on the Mode pins, the strength of these pullups is not tested or guaranteed. Consequently, you should NEVER leave the Mode pins floating.

Additionally, when measuring the level of the Mode pins, you should always measure the voltage levels at the FPGA package. This ensures that a connection error did not occur between the driving source and the FPGA Mode pins. Please refer to the chart below for information about valid logic levels.

DEVICES.................| VOLTAGE..| STANDARD.| DESCRIPTION

................................| (VCC)..........|......................|

================================================================

XC4000...................|.......5...........|.....TTL............| 0: A logic Low in TTL

(A/D/H/L/E/EX).....|....................|.......................| should be < 0.5 Volts.

Spartan....................|....................|.......................| A pull-down of 4.7KOhm is

XC3000 (A/L)..........|.....................|.......................| recommended.

XC5200...................|.....................|.......................| 1 : A logic high in TTL should be > 4.0 Volts. A pullup of 3.3KOhm is recommended.

=================================================================

XC4000X.................|......3.3..........|....LVTTL........| 0: A logic Low in LVTTL

(XL/XLT/XLA/XV)...|.....................|.......................| should be < 0.5 Volts.

Spartan-XL..............|......................|.......................| A pull-down of 4.7KOhm is recommended.

................................|......................|.......................| 1 : A logic High in LVTLL should be > 3.0 Volts. A pullup of 3.3KOhm is recommended.

Data pin(s) [DIN or D<7:0>] are not correctly connected on the board

Serial Mode:

If you are configuring in serial mode, probe the DIN pin directly at the FPGA package pin. Verify that the configuration data is reaching the FPGA's pin. Probing a trace or the data source is not sufficient proof that the data is reaching the FPGA.

Parallel Mode:

If you are configuring in parallel mode, it is unlikely that all eight data pins are connected incorrectly, or that only one or a few of the pins are incorrect without causing a DataFrame Error (INIT goes Low - (Xilinx Answer 8158)), these conditions can result when no configuration data reaches the FPGA. Probe the Data pins directly at the FPGA package pins. Verify that the configuration data is reaching the FPGA's pins. Probing a trace or the data source is not sufficient proof that the data is reaching the FPGA.

CCLK is not transitioning or is connected incorrectly

Probe the CCLK pin directly at the FPGA package pin, as well as the source (if in slave mode) or the destination (if in master mode). Verify that the clock is transitioning and is well within the timing specifications for the clock load. If the device is in a master mode, try setting the CCLK to SLOW in the configuration options. If the device is in a slave mode, try slowing down the CCLK.

Boundary Scan has been invoked

From the moment of power-up, Boundary Scan (JTAG) operations are available within the FPGA. These operations may be inadvertently invoked by movement on the TCK pin, and can take the FPGA out of configuration mode. Verify that the TMS is High and that the TCK is not moving. If your application uses a free-running clock on TCK, ensure that TMS is a strong logic `1', and recycle the PROG pin to restart configuration.

NOTE: This solution applies ONLY to Express Mode and the Asynchronous Peripheral (called "Peripheral" in the XC5200) Modes.

The Chip Selects (CS0 and CS1) are not set properly

Express Mode:

The CS1 is the Chip Select that enables the FPGA for configuration in the Express Mode. If the CS1 is Low, the FPGA ignores all CCLK transitions and will not configure. If this is the lead device in a daisy-chain or a single device, attach a pullup resistor to CS1 or make adjustments to whatever logical device is driving this input to bring it to a Logic High. If this is a secondary device in a daisy-chain, investigate the reason that the preceding device did not bring its DOUT High since this should be driving the CS1. CS0 is not used for Express mode configuration.

Peripheral/Asynchronous Peripheral:

The Chip Selects CS0 and CS1 must be set to a Logic Low and a Logic High, respectively, for the FPGA to accept configuration data in the peripheral mode. Verify the logic state of these pins.

The PROG or INIT pin is Low (for all devices EXCEPT the XC3000 family):

The PROG pin is an Active Low input that forces the FPGA to clear its configuration memory. The INIT pin is a bidirectional signal before and during configuration; if this pin is held Low, it will delay configuration. Verify that these signals are not continuously driven Low on the board. If they are, take the appropriate action to release them so that configuration may begin.

The RESET or PWRDN pin is Low: (for XC3000 devices):

The RESET pin is an Active Low input that is a global reset after configuration, but will restart the configuration process if active during configuration. As a result, configuration will not begin if RESET is Low. The PWRDN pin is an Active Low input that powers down the device. PWRDN must be High before and during configuration. Verify the drivers to these signals, and ensure that they are at the correct level so that configuration can begin.

The FPGA is not properly powered

If an FPGA is not properly powered, it will not function at all. However, do not dismiss this possibility since a single mis-connection can inadvertently prevent normal operation. Check every VCC, GND, and configuration-related pin (PROG, INIT, DONE (D/P), CCLK, Mode pins, etc.) for short circuits.

AR# 8213
创建日期 08/21/2007
Last Updated 03/06/2013
状态 Active
Type 综合文章