General Description: My netlist can be mapped successfully into a 4KXL part, but MAP fails with the following error when I target a 4KXLA part:
FATAL_ERROR: OldMap:x45maclb.c:204:184.108.40.206 - Unknown input pin Q for CLB LATCH primitive. Process will terminate.
All the pin types in the LDCE_1 latches were incorrectly defined to be "B" instead of "I" or "O". LDCE_1 is not listed as a primitive in the FPGA Express library. Because of this, it is treated as a black box when it is instantiated. Verilog does not require pin directions to be defined for these types of instantiations, and since FPGA Express has no knowledge of this component, it will default to bidirectional. To solve this problem, simply define the LDCE_1 module as follows: