UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 8263

Virtex CLKDLL VHDL Simulation - DLL outputs are not toggling (no output); CLKIN is delayed

Description

Keywords: CLK0, CLK2X, output, stuck, no switching, DLL, SimPrim

Urgency: Standard

General Description:
I am using the CLKDLL and performing a VHDL back-end timing simulation using the Xilinx 2.1i tools. The CLKIN to the DLL is delayed for hundreds of nanoseconds, or has a signal that is much slower than the specified frequency range for the DLL by hundreds of nanoseconds. After this period of time, CLKIN changes to a frequency within the range of the DLL, but the outputs are delayed. Also, the outputs, such as CLK0 and CLK2X, are not toggling.

解决方案

This is a SimPrim CLKDLL model problem. The model is delayed in a "wait" statement when the CLKIN pin is stimulated as described. You can "comment out" the following line (line 1841) in the simprim_VITAL.vhd file:

wait;

This will be fixed in the next major release of the Xilinx software.
AR# 8263
创建日期 08/31/2007
Last Updated 08/25/2003
状态 Archive
Type ??????