General Description: In version 3.3.1 of FPGA Compiler II, a bug has been identified where a multiple driver error may occur in Translate (NGDBUILD). When using a bidirectional pad, the EDIF may be generated incorrectly; the netlist will contain both an IOPAD and IPAD on the same net. The following error will occur:
ERROR:NgdHelpers:336 - logical net "bidir" has both active and tristate drivers ERROR:NgdHelpers:346 - input pad net "bidir" has an illegal connection
This error should only occur when the bidirectional signal is used to drive clock pins and therefore has had a BUFG instantiated on the input side of that port.
One resolution is to disable the global buffer insertion in the Express Constraints Editor. Under the Ports tab, set the DEFAULT Global Buffer setting to DONT USE. Due to an issue documented in (Xilinx Solution 4791), you must change this setting on the top line (default), not the bidirectional port itself.
Any global buffers you do wish to have inserted must be specified individually in this column under their respective port listing, or instantiated in the HDL code.
Note that this solution will not work if you do wish to have the BUFG inserted on the input of the bidirectional port in question.
Another resolution is to instantiate all the components of the bidirectional I/O. This means instantiating the IOPAD (pin name is IOPAD), BUFG, and OBUFT (or variation thereof) in your HDL source. You must also remove that port from the top level port declaration so Express does not try to insert I/O components. See (Xilinx Solution 6085) for more details about instantiating pads.