AR# 8350


JTAG, BSDL - What is BSDL, and how do I read a BSDL file?


What is the origin of BSDL? How is BSDL used, and how is it read?


Several data formats have emerged that allow IEEE 1149.1 to be successful and well-supported by tools. Boundary-Scan Description Language (BSDL) is one of them.

Current BSDL files are available for download at:

The following excerpt is taken from the Texas Instruments web site at:


In 1990, the IEEE 1149.1 standard was approved, and implementation of the standard accelerated. As more people became aware of and used the standard, the need for a standard method for describing IEEE 1149.1-compatible devices was recognized. The IEEE 1149.1 working group established a subcommittee to develop a device description language to address this need.

The subcommittee has since developed and approved an industry standard language called Boundary-Scan Description Language (BSDL). BSDL is a subset of VHDL (VHSIC Hardware Description Language) that describes how IEEE 1149.1 is implemented in a device and how it operates. BSDL captures the essential features of any IEEE 1149.1 implementation. BSDL was approved in 1994 as IEEE Std. 1149.1b.

The IEEE 1149.1 is a structured design-for-test approach well-suited for tools and automation. Tools developed to support the standard can control the TAP (Test Access Port) if they know how the boundary-scan architecture was implemented in the device. Tools can also control the I/O pins of the device. BSDL provides a standard machine and human-readable data format for describing how IEEE 1149.1 is implemented in a device.

How is a BSDL file used?

Many IEEE 1149.1 tools already on the market support BSDL as a data input format. These tools offer different capabilities to customers implementing IEEE 1149.1 into their designs, including board interconnect Automatic Test Pattern Generation (ATPG) and Automatic Test Equipment (ATE).

When you use tools that support BSDL, you can often obtain BSDL from your semiconductor vendor. This can result in significant time and cost savings.

Teradyne estimates that creating in-circuit test patterns for a leading microprocessor normally may require as much as seven weeks' time:

- One week to study the device

- Four weeks to develop in-circuit test patterns

- Two weeks to verify the patterns on ATE

The development cost estimate for this approach is $14,000.

If the microprocessor supports IEEE 1149.1, and the BSDL is supplied by the vendor, the time to develop in-circuit test patterns is less than two hours (less than $100) using today's tools.

How to read BSDL files

A BSDL description for a device consists of the following elements:

- Entity descriptions

- Generic parameter

- Logical Port description

- Use statements

- Pin Mapping(s)

- Scan Port identification

- Instruction Register description

- Register Access description

- Boundary Register description

Entity descriptions: The entity statement names the entity, such as the device name (e.g., SN74ABT8245). An entity description begins with an entity statement and terminates with an end statement.

entity XYZ is

{statements to describe the entity go here}

end XYZ

Generic parameter: A generic parameter is a parameter that may come from outside the entity, or it may be a default parameter, such as a package type (e.g., "DW").

generic (PHYSICAL_PIN_MAP : string := "DW");

Logical port description: The port description gives logical names to the I/O pins (system and TAP pins) and denotes their nature to be input, output, bidirectional, etc.

port (OE:in bit;

Y:out bit_vector(1 to 3);

A:in bit_vector(1 to 3);

GND, VCC, NC:linkage bit;

TDO:out bit;

TMS, TDI, TCK:in bit);

Use statements: The use statement refers to external definitions found in packages and package bodies.

use STD_1149_1_1994.all;

Pin mapping(s): Pin-mapping provides a mapping of logical signals onto the physical pins of a particular device package.

attribute PIN_MAP of XYZ : entity is


constant DW:PIN_MAP_STRING:=

"OE:1, Y:(2,3,4), A:(5,6,7), GND:8, VCC:9, "&

"TDO:10, TDI:11, TMS:12, TCK:13, NC:14";

Scan port identification: The scan port identification statements define the device's TAP.

attribute TAP_SCAN_IN of TDI : signal is TRUE;

attribute TAP_SCAN_OUT of TDO : signal is TRUE;

attribute TAP_SCAN_MODE of TMS : signal is TRUE;

attribute TAP_SCAN_CLOCK of TCK : signal is (50.0e6, BOTH);

Instruction register description: The instruction register description identifies the device-dependent characteristics of the instruction register.

attribute INSTRUCTION_LENGTH of XYZ : entity is 2;

attribute INSTRUCTION_OPCODE of XYZ : entity is

"BYPASS (11), "&

"EXTEST (00), "&

"SAMPLE (10) ";

attribute INSTRUCTION_CAPTURE of XYZ : entity is "01";

Register access description: The register access defines which register is placed between TDI and TDO for each instruction.

attribute REGISTER_ACCESS of XYZ : entity is "BOUNDARY (EXTEST, SAMPLE), "&


Boundary register description: The boundary register description contains a list of boundary-scan cells, along with information regarding the cell type and associated control.

attribute BOUNDARY_LENGTH of XYZ : entity is 7;

attribute BOUNDARY_REGISTER of XYZ : entity is "0 (BC_1, Y(1), output3, X, 6, 0, Z), "&

"1 (BC_1, Y(2), output3, X, 6, 0, Z), "&

"2 (BC_1, Y(3), output3, X, 6, 0, Z), "&

"3 (BC_1, A(1), input, X), "&

"4 (BC_1, A(2), input, X), "&

"5 (BC_1, A(3), input, X), "&

"6 (BC_1, OE, input, X), "&

"6 (BC_1, *, control, 0)";

Additional information about BSDL and SVF files is available at:

A BOUNDARY_REGISTER is a bit more complicated.

Each register in the boundary scan chain from TDO to TDI is described in this section. Normally, inputs have one register, outputs have two registers, and bidirectional I/Os have three registers (input, control, and output3).

The fields within the brackets are:

Field 1: Cell Type, as defined by the standard (all ICBD cells are BC_2 or BC_4).

Field 2: Port Name; control registers do not specify a port name.

Field 3: Cell Function; input, output3, or control (as defined by standard).

Field 4: Safe Value; specifies what value should be loaded into the register when the software might otherwise choose a value at random.

(Fields 5 - 7 are needed only for output registers.)

Field 5: Control Cell Number; specifies the control register that drives the output enable for this port.

Field 6: Disable Control Value; the value that is loaded into the control register to disable the driver.

Field 7: Disable Value; indicates what occurs when the driver is disabled.

AR# 8350
日期 12/15/2012
状态 Active
Type 综合文章
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