AR# 8372

2.1i COREGEN, C_IP4: Virtex Asynchronous FIFO Verilog simulation "ERROR: Module or primitive (ASYNC_FIFO_V1_0) not defined"

描述

Urgency: standard

General Description:

There is a case mismatch in the module and port name references in the XilinxCoreLib

asynch_fifo_v1_0.v behavioral model and the .VEO file generated for the Asynchronous

FIFO. The asynch_fifo_v1_0.v behavioral model references the "async_fifo_v1_0" module

name and port list in lowercase, while the instantiation template section of the .VEO file

generated by Coregen references both the module name and all of the ports in UPPERCASE.

This may cause errors similar to the following when simulating:

"ERROR! Module or primitive (ASYNC_FIFO_V1_0) not defined"

After correcting this problem multiple errors may be found with the port names:

"ERROR! Input, output or inout (din) not defined in port list

Again, this is due to mismatched case in the port name references used in several

modules in the model, including the ASYNC_FIFO_V1_0 module.

解决方案

The solution is to edit the async_fifo_v1_0.v model in XilinxCoreLib and change the

module name and port names in the async_fifo_v1_0 instantiation block to upper case

to match the way these are referenced in the auto-generated .VEO file.

In other words, starting on line 2460, change:

module async_fifo_v1_0 (din, wr_en, wr_clk, rd_en, rd_clk, ainit, dout,

full, empty, almost_full, almost_empty, wr_count,

rd_count, rd_ack, rd_err, wr_ack, wr_err);

to:

module ASYNCH_FIFO_V1_0(DIN, WR_EN, WR_CLK, RD_EN, RD_CLK, AINIT, DOUT,

FULL, EMPTY, ALMOST_FULL, ALMOST_EMPTY, WR_COUNT,

RD_COUNT, RD_ACK, RD_ERR, WR_ACK, WR_ERR);

In addition, starting at line 2509, you must change this section:

input [C_DATA_WIDTH-1 : 0] din;

input wr_en;

input wr_clk;

input rd_en;

input rd_clk;

input ainit;

//output [C_READ_DATA_WIDTH-1 : 0] dout;

output [C_DATA_WIDTH-1 : 0] dout;

output full;

output empty;

output almost_full;

output almost_empty;

output [C_WR_COUNT_WIDTH-1 : 0] wr_count;

output [C_RD_COUNT_WIDTH-1 : 0] rd_count;

output rd_ack;

output rd_err;

output wr_ack;

output wr_err;

to:

input [C_DATA_WIDTH-1 : 0] DIN;

input WR_EN;

input WR_CLK;

input RD_EN;

input RD_CLK;

input AINIT;

//output [C_READ_DATA_WIDTH-1 : 0] dout;

output [C_DATA_WIDTH-1 : 0] DOUT;

output FULL;

output EMPTY;

output ALMOST_FULL;

output ALMOST_EMPTY;

output [C_WR_COUNT_WIDTH-1 : 0] WR_COUNT;

output [C_RD_COUNT_WIDTH-1 : 0] RD_COUNT;

output RD_ACK;

output RD_ERR;

output WR_ACK;

output WR_ERR;

For information on additional modifications required, see (Xilinx Solution #8374)

This problem is fixed in the following tactical patch:

http://www.xilinx.com/txpatches/pub/swhelp/coregen/c_ip4_patch1.tar.gz (UNIX), or

http://www.xilinx.com/txpatches/pub/swhelp/coregen/c_ip4_patch1.zip (PC)

Extract the patch to your Xilinx directory.

本答复记录是否对您有帮助？

AR# 8372
日期	07/06/2010
状态	Archive
Type	综合文章

的页面

AR# 8372

2.1i COREGEN, C_IP4: Virtex Asynchronous FIFO Verilog simulation "ERROR: Module or primitive (ASYNC_FIFO_V1_0) not defined"

描述

解决方案

应用

产品

开发者专区

技术支持

关于 Xilinx