AR# 8390

Signal Integrity (all FPGAs) - How does signal placement affect the number of SSOs a device can support before ground bounce becomes a problem?


General Description:

Does it make any difference which bank the signals are in? For example, assume I have 8 signals: either 4 in bank1 and 4 in bank2, or 8 in bank1. Is ground bounce more likely to occur when all signals are in bank1? It seems that the problem is with disturbances in the ground plane, and because there is only one ground plane, signal placement should not matter.


For a detailed discussion about handling SSOs, please refer to (Xilinx XAPP689): "Managing Ground Bounce in Large FPGAs."

Signal placement matters because, at the very high frequencies at which today's FPGAs switch, minimizing the distance a signal must traverse across a reference plane is crucial. The number of SSOs that can be safely handled is directly related to the number of and proximity of effective VCCO/GND pairs (note that the number of effective pairs is not the same as the actual number of pairs; the number of effective pairs is outlined in device data sheets).

It's always better to spread signals out because this effectively increases the ratio of VCCO/GND pairs per I/O. An important point to remember is that the VCC and GND planes are not ideal conductors, in the sense that a high-frequency signal takes a finite amount of time to propagate from one point on the plane to another.

AR# 8390
日期 12/15/2012
状态 Active
Type 综合文章