You are using a deprecated Browser. Internet Explorer is no longer supported by Xilinx.
2.1i Foundation Logic Simulator -Timing simulation of Virtex DLL fails when the input frequency is higher than 100MHz
Keywords: FNDTN, Virtex, CLKDLL, timing, simulation
When I perform a timing simulation of a Virtex CLKDLL, the CLKDLL functions properly to a specified clock frequency, then fails to output
the correct (or any) frequency.
This result is caused by lump sum modeling. This issue may be resolved in two ways:
1. Use a simulator that supports transport or transparent switches. This permits the small clock pulses to pass through the logic, which allows the CLKDLL to simulate correctly.
2. Set the environment variable "XIL_PP_OPTIMIZE" to true:
Then, regenerate the timing simulation files.