UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

的页面

AR# 8420

Synplify - How do I change the BUFG limit from 4 to 8 for a Spartan-XL design? (BUFGLS)

Description

Keyword: Spartan-XL, Synplicity, clock, infer, global, buffer 

 

 

 

General Description: 

Synplify limits global buffer insertion to four. However, in some architecture (such as Spartan-XL), a design can use up to eight BUFGLS. How do I change BUFG limit from 4 to 8 for these architectures?

解决方案

Set the following attribute in the .sdc file to increase the limit of BUFG insertion in Synplify: 

 

define_global_attribute xc_global buffers (8)

AR# 8420
日期 05/14/2014
状态 Archive
Type 综合文章