The path described previously is an SRLUT-to-flip-flop, which is contained in a SLICE. Therefore, this is an internal clock-to-clock path within the SLICE, and this path is not currently analyzed.
This delay is fixed and can be located in the device data sheet under "Switching Characteristics".
| AR# 8477 | |
|---|---|
| 日期 | 12/15/2012 |
| 状态 | Active |
| Type | 综合文章 |