The Virtex devices have four DLLs, and the Virtex-E devices have Eight DLLs. How many of these DLLs can be cascaded together in one chain?
The limit depends on the effective jitter that results from the cascaded CLKDLLs. Jitter is additive through our DLLs. You must verify that your cascaded DLL scheme is in spec, so that it does not violate the Input Clock Jitter Tolerance of the final CLKDLL.
For example, suppose you have two CLKDLLHFs cascaded together. If your input clock has a jitter +/- 100ps, your output jitter will be 100ps + 60ps = +/- 160ps after passing through the first CLKDLL; this exceeds the allowable Input Clock Jitter Tolerance for a Virtex-E CLKDLLHF (+/- 150ps).
Also, be certain to verify that you are meeting the Input/Output Maximum/Minimum Frequencies of the CLKDLLs.