(Xilinx Answer #7372) : 2.1i Virtex PAR - PC only crash occurs after "Starting the placer".
(Xilinx Answer #7249) : 2.1i 4000XL/XV PAR - Dr Watson during routing. Access Violation (0xc0000005), Address: 0x0024b0b1.
(Xilinx Answer #7734) : 2.1i Virtex PAR - The .par results file reports incorrect number of logic levels
(Xilinx Answer #7316) : 2.1i Virtex PAR - Placer has been enhanced to use MAXSKEW preference to assign secondary global clock buffers for external clock nets.
(Xilinx Answer #6690) : 2.1i Virtex PAR - FATAL_ERROR:Place:xvkapanal.c:1860:1.1.2.21.2.1
(Xilinx Answer #6739) : 2.1i Virtex PAR - Virtex design is taking too long to route PWR/GND signals.
(Xilinx Answer #7335) : 2.1i SpartanXL PAR - PAR fails to produce consistent results when running a cost table twice.
(Xilinx Answer #6953) : 2.1i Virtex PAR - Virtex designs with area constraints may run out of memory during placement.
(Xilinx Answer #7064) : 2.1i Virtex PAR - Router terminates with Segmentation fault during PWR/GND routing.
(Xilinx Answer #7350) : 2.1i PAR - PAR does not cleanup low-end results when running turns engine (ignores -s)
(Xilinx Answer #7345) : 2.1i Virtex PAR - Placer leaves source pin of high fanout net unplaced, leading to router crash.
(Xilinx Answer #7078) : 2.1i Virtex PAR - Placer ignores list constraint involving IOB.
(Xilinx Answer #7342) : 2.1i SpartanXL PAR - FATAL_ERROR:Route:basrtsanity.c:241:1.1.2.2 -Process will terminate.
(Xilinx Answer #726) : 2.1i Design Manager: New behavior for UCF declaration introduced.
(Xilinx Answer #6554) : 2.1i Design Manager - Running pld_dsgnmgr through Mentor DM or using the Design Manager option from Exemplar's P&R tab, can not choose options for implementation.
(Xilinx Answer #7328) : 2.1i Design Manager - DM Overwrite Last Version does not work on win95/98 & WS
(Xilinx Answer #7329) : 2.1i FPGA Editor - ERROR:Portability:90 - Command line error: Switch '-usedpin' is unexpected.
(Xilinx Answer #7334) : 2.1i FPGA Editor - Busy cursors are not used on many long processes.
COREGEN
(Xilinx Answer #8497): 2.1i COREGEN - Not all EDIF files may be copied over when generating cores made up of multiple EDIF files.
(Xilinx Answer #7151) : 2.1i Foundation COREGEN - "Line: 3 Wrong number of fields BUS" on modules during symbol generation.
(Xilinx Answer #6853) : 2.1i Foundation COREGEN - Unexpanded block error ... because one or more pins on the block ... were not found.
(Xilinx Answer #7397) : 2.1i Foundation COREGEN - Virtex Variable Parallel Multiplier optional pins appear in a Foundation symbol even when not requested.
(Xilinx Answer #6890) : 2.1i Foundation COREGEN - Coregen may not be able to locate the Foundation install directory on Windows.
SPEED FILES
(Xilinx Answer #8294): 2.1i Virtex-E Speed Files - New speed files are available for Virtex-E.
(Xilinx Answer #8117) : 2.1i Speed Files - There are several speed file changes available in Service Pack 3.
(Xilinx Answer #7327) : 2.1i Virtex Speed Files - New Virtex Speed files are available in 2.1i Service Pack 1.
(Xilinx Answer #7330) : 2.1i XC4000XV Speed Files - The 2.1i Service Pack 1 Update contains Preliminary XC4000XV speed data.
(Xilinx Answer #7352) : 2.1i SpartanXL Speed Files - Updated speed files are available for -5 Preliminary speed grades.
PACKAGE FILES
(Xilinx Answer #8296) : 2.1i Spartan2 Package Files - The TQ144 Package has been added for Spartan2.
(Xilinx Answer #8298) :2.1i Virtex-E Packages - The XV600E FG900 and XV1000E FG1156 packages have bad banking information.
(Xilinx Answer #8118) : 2.1i Spartan2 Package Files - New package files are available with Service Pack 4.
(Xilinx Answer #7736) : 2.1i Package Files - Incorrect location for Spartan40XL BG256 DONE pin specified in the pad report.