We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!


AR# 8543

3.x FPGA Express - "Warning: Cannot link to cell 'cell_name' to its reference design 'component_name'. (FPGA-LINK-2)" (Black boxes)


Keywords: cannot, link, cell, reference, design, warning, FPGA, 2

Urgency: Standard

General Description:
During the synthesis of a file, a number of warnings similar to the following are displayed:

"Warning: Cannot link to cell 'cell_name' to its reference design 'component_name'.

where "component_name" is an instatiated component.


This warning is normal for all instantiated components in your code. If the component is a primitive, no action is needed.

NOTE: For 3000, 4000e, 5200 and 9500:
If the component is a macro, you must copy the .xnf netlist from the Fndtn\Synth\xilinx\macros\<device family> to your project directory. To find components that are macros, check the Libraries Guide.
AR# 8543
日期 08/11/2003
状态 Archive
Type 综合文章