AR# 8647

2.1i COREGEN, C_IP4: Asynchronous FIFO model does not appear to increment WR_COUNT properly in Verilog-XL simulation


Keywords: asynchronous fifo, wr_count

Urgency: hot

General Description:

The Asynchronous FIFO WR_COUNT output does not appear to increment properly
in Verilog-XL behavioral simulation. It has been observed typically at the start of a simulation,
but is not limited to this.

The problem appears to be specific to the Verilog-XL simulator, as it does not reproduce in
SILOS or ModelSIM simulators.


This problem is fixed in the following tactical patch: (UNIX), or (PC)

Extract the patch to your Xilinx directory.
AR# 8647
日期 09/05/2001
状态 Archive
Type 综合文章