UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 8647

2.1i COREGEN, C_IP4: Asynchronous FIFO model does not appear to increment WR_COUNT properly in Verilog-XL simulation

Description

Keywords: asynchronous fifo, wr_count

Urgency: hot

General Description:

The Asynchronous FIFO WR_COUNT output does not appear to increment properly
in Verilog-XL behavioral simulation. It has been observed typically at the start of a simulation,
but is not limited to this.

The problem appears to be specific to the Verilog-XL simulator, as it does not reproduce in
SILOS or ModelSIM simulators.











解决方案

This problem is fixed in the following tactical patch:

http://www.xilinx.com/txpatches/pub/swhelp/coregen/c_ip4_patch1.tar.gz (UNIX), or
http://www.xilinx.com/txpatches/pub/swhelp/coregen/c_ip4_patch1.zip (PC)

Extract the patch to your Xilinx directory.
AR# 8647
创建日期 02/18/2000
Last Updated 09/05/2001
状态 Archive
Type 综合文章