We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 8713

9.1i Virtex MAP - "Error:DesignRules:365 - Blockcheck: Improper DLL feedback loop"


The following error appears when I connect DLLs: 


"ERROR:DesignRules:365 - Blockcheck: Improper DLL feedback loop. Signal is driving pin IN of comp bufg1. Since pin CLKFB of DLL dll1 is driving by an GCLKIOB, its output must drive the O pin of IOB."


If a DLL is used in conjunction with external feedback, no output of the DLL can be used to drive internal logic. This rule enables the software to determine which DLL clock output sources the CLKFB pin. 


For more information on valid DLL connections, please refer to Xilinx Application Note "Using the Virtex Delay-Locked Loop" (Xilinx XAPP132). Note that a single DLL is used to provide off-chip feedback, and a separate DLL is used to create internal clocks.

AR# 8713
日期 05/14/2014
状态 Archive
Type 综合文章