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AR# 8788

C_IP4 COREGEN: DA_FIR_V1_0: Warning! Port sizes differ in port connection (port 4) [Verilog-PCDPC]


Keywords: Distributed Arithmetic FIR Filter, Verilog

A warning similar to the following may be seen during Verilog behavioral simulation
of the CORE Generator DA FIR Filter for Virtex:

"Warning! Port sizes differ in port connection (port 4) [Verilog-PCDPC]
"top_dafir.v", 111: DIN"

Although this type of warning is typically associated with a user error in connecting
up the interface ports of interconnected modules, another possible cause in the
case of the CORE Generator DA FIR module is a bug in the ordering of the
customization parameters being passed in the VEO template file. If the latter is
the cause, the problem is that some parameters passed in the module declaration
section of the VEO template for the Virtex DA FIR Filter have been inadvertently
switched around.

Specifically, C_COEFF_WIDTH and C_DATA_WIDTH, the 3rd and 5th parameters in the
Verilog model are passed as the 4th and 6th parameters of the declaration template
in the .VEO file. Parameters 3 & 4 appear to have been swapped with parameters 5 & 6.


The parameter list in the VEO is excerpted below with annotations
(delimited with a "//" comment marker) added to indicate the parameter
in the behavioral model to which the value being passed.

// synopsys translate_off

C_DA_FIR_V1_0 #(
1, // C_BAAT
0, // C_COEFF_WIDTH parameter #3
16, // C_COEFF_TYPE parameter #4
0, // C_DATA_WIDTH parameter #5
10, // C_DATA_TYPE parameter #6
0, // C_FILTER_

Also, the following related definitions for data types of "signed" and
"unsigned" are also declared in the model:

`define c_signed 0 // for c_data_type
`define c_unsigned 1

You can determine the correct settings for the VEO parameters
by reviewing the corresponding settings in the XCO file for the
generated core (the
XCO for each core is usually written to your project directory).

# Xilinx CORE Generator 2.1i
# Username = karlton
# COREGenPath = h:\f2_1i\coregen
# ProjectPath = H:\f2_1i\Active\projects\testvir
# ExpandedProjectPath = H:\f2_1i\Active\projects\testvir
SET BusFormat = BusFormatAngleBracket
SET SimulationOutputProducts = VHDL Verilog
SET ViewlogicLibraryAlias = "karlton"
SET XilinxFamily = Virtex
SET DesignFlow = VHDL
SET FlowVendor = Synopsys
SELECT Distributed_Arithmetic_FIR_Filter Virtex Xilinx,_Inc. 1.0
CSET coefficient_file = H:\f2_1i\coregen\data\vsdafir.coe
CSET coefficient_data_type = signed <-------------------------------------
CSET number_of_taps = 10
CSET register_output = FALSE
CSET optimize_coefficients = TRUE
CSET component_name = vsdafir
CSET zero_packing_factor = 2
CSET impulse_response = non_symmetric
CSET number_of_channels = 1
CSET filter_type = single_rate_fir
CSET coefficient_width = 16 <-----------------------------------
CSET input_data_width = 10 <-------------------------------------
CSET input_data_type = signed <-------------------------------------


Based on this, the relevant lines in the VEO template can be corrected as follows
so that COEFF_WIDTH is set to 16, COEFF_TYPE is set to 0 (signed),
C_DATA_WIDTH is set to 10, and C_DATA_TYPE is set to 0 (signed):

C_DA_FIR_V1_0 #(
1, // C_BAAT
16, // C_COEFF_WIDTH parameter #3 - corresponds to CSET coefficient_data_width=10
0, // C_COEFF_TYPE parameter #4 -- corresponds to SIGNED data type for coefficients -
10, // C_DATA_WIDTH parameter #5 -- corresponds to CSET input_data_width = 16
0, // C_DATA_TYPE paramepter #6 -- corresponds to CSET input_data_type = signed
AR# 8788
日期 09/10/2008
状态 Archive
Type 综合文章