UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 8796

JTAG - What is the maximum JTAG clock (TCK) frequency for a Xilinx device?

Description

What is the maximum JTAG clock (TCK) frequency for Xilinx devices?

解决方案

The maximum configuration clock rate varies depending on the device family, as follows:

XC4000 - 5 Mhz

XC9500 - 10 Mhz

Virtex - 33 Mhz

For more information, refer to the appropriate BSDL file.

Examples:

attribute TAP_SCAN_CLOCK of TCK : signal is (1.00e+07, BOTH);

This indicates that the maximum frequency is 10 Mhz.

attribute TAP_SCAN_CLOCK of TCK : signal is (33.0e6, BOTH);

This indicates that the maximum frequency is 33 Mhz.

For information on the maximum TCK speed for Xilinx configuration cables, please refer to (Xilinx Solution 9803).

AR# 8796
创建日期 08/21/2007
Last Updated 12/15/2012
状态 Active
Type 综合文章