You may see MAP warnings similar to the following about the the higher order output bits of a CORE Generator Single Port Block Memory being unconnected with Single Port Block memories wider than 16 bits:
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB4 of comp u1/BU0 is not connected. WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB5 of comp u1/BU0 is not connected. WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB6 of comp u1/BU0 is not connected.
These warnings are normal when you generate a Single Port Block ROM which is wider than 16 bits. The reason they may be seen is because the CORE Generator implements such wide data word Single Port memory functions in a novel way that results in significant savings in LUT resources. The methodology used is described on p. 9 of XAPP130:
Basically it involves interleaving the memory space, setting the LSB of the address bus of Port A to 1 (VCC ), and the LSB of the address bus of Port B to 0 (GND).
In conjunction with this, the output of the wide memory is generated by concatenating the bits from the two dual port output ports together. Usually all 16 bits from one of the ports are used first, and the remaining bits are implemented using the LSBs of the second output port. This may result in some MSBs on the second output port being unconnected.