General Description: If MTI issues the following warning:
WARNING: top.vhf(44): No default binding for component: "decode". (No entity named "decode" was found)
Where decode is the name of the CoreGEN CORE created, MTI is unable to locate the simulation module for the core. The solution for VHDL and Verilog can be found below.
CoreGEN VHDL simulation models are linked to the design using configuration statements. A majority of the configuration information is include in the CoreGEN instantiation template which was generated when the core was created. In the project directory there should be a file named core.vho, this file contains the CORE configuration information.
In a schematic design containing a CoreGEN macro, a hierarchical configuration statement must be added to the testbench which provides the stimulas for the schematic.
Here is a template of the configuration that must be added to the bottom of the testbench:
CONFIGURATION <cfg_name> OF <testbench_entity> IS FOR <testbench_arch> for all : <instantiated_comp> use entity work.<entity>(<architecture>); for <architecture> for all : <core_name> use entity XilinxCoreLib.C_DECODE_BINARY_V1_0(behavioral) configuration information provided in the coregen instantiation template end for; end for; end for; END FOR; END TOP_cfg;
CoreGEN Verilog simulation models are linked to the design using 'include statements. This information is include in the CoreGEN instantiation template which was generated when the core was created. In the project directory there should be a file named core.veo, this file contains the CORE configuration information.
To incorporate this information in the Foundation ISE project follow these steps: 1- rename the core.veo file to core.v and add it to the project. 2- select the core.v file and double click on the "Create Schematic Symbol" process. 3- when asked if you should write over the existing symbol select yes. 4- add the symbol to the schematic.
This will allow you to preform functional simulation and implement your design.