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AR# 889

ModelSim (MXE, SE, PE) - Vlog "WARNING: [TSCALE] - Module '...' does not have a `timescale directive in effect, but previous modules do." (Verilog)


Keywords: timescale, Verilog, Vsim, Vlog

Urgency: Standard

General Description:
When simulating with ModelSim Vlog, I encounter the following warning:

WARNING: [TSCALE] - Module '...' does not have a `timescale directive in effect, but previous modules do.

What does this warning mean?


The `timescale can be declared in any file.

The UNISIMS has 100ps/10ps.
The SIMPRIMS has 1ps/1ps.
The glbl.v has 100ps/10ps.

The smallest precision of all the timescale directives determines the time unit of the simulation. For example,

`timescale 1 ns / 10 ps
module1 ();

`timescale 100 ns / 1 ns
module2 ();

`timescale 1 ps / 100 fs
module3 ();

The first timescale indicates that the time units for "module1" are in multiples of 1 ns and are precise to 10 ps. Thus, the smallest timestep for the simulator is 10 ps.

The second timescale is 100 ns/1 ns. Since 1 ns is greater than 10 ps, the smallest timestep remains 10 ps.

The third timescale is 1 ps/100 fs. Since 100 fs is smaller than 10 ps, the smallest simulator timestep now becomes 100 fs.

The `timescale compiler directive is optional. Designs that do not contain this require no modification, and the default of 1 ns/1 ns is used.

However, if the design includes a `timescale compiler directive for any one module definition, then all other module definitions require this as well. If this does not happen, ModelSim Vlog issues this warning.
AR# 889
日期 05/10/2004
状态 Active
Type 综合文章