General Description:
In Timing Analyzer, when I select Analyze -> Analyze Against User Defined Paths by Defining Clock and I/O Timing, the slave clock "CLKB" of an LVDS pair is not available as a port for creating offset constraints.
This will be fixed in the next major software release (5.1i).
AR# 8963 | |
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日期 | 01/18/2010 |
状态 | Archive |
Type | 综合文章 |