General Description: Leonardo Spectrum supports both "Attributes" and "Optimization" variables. Attributes can be set in the VHDL or Verilog code. They can also be set using the "set_attribute" command from the Leonardo Spectrum command line interface.
Attributes will tag a netlist object (such as an instance, net or port) with a property. A shortcut command is available for setting certain attributes. For example, the command "arrival_time" really sets the attribute "set_attribute -name arrival time."
See Leonardo Spectrum's "Technology Guide" for more information. This is provided as a PDF file in the Leonardo installation directory. You can view it from the "Help" pull-down menu: Help -> View User Manuals -> Technology Guide.
All the variables can be viewed by typing "help -var" at the command line, or by launching the "Variable Editor" from the "Tools" pull-down menu. Please refer to the user manuals for a complete list of attributes.
解决方案
The following is a list of Xilinx-specific attributes:
Assigning the BUFGDLL cell to a clock port: > PAD clk BUFGDLL or > set_attribute clk -name PAD -value BUFGDLL -port
Assigning a single register to IOB: > set_attribute reg_state(4) -instance -name IOB -value TRUE
Set a Max Fanout on a net: > set_attribute -net sensor2_int -name max_fanout -value 3
Control Block RAM Inference on an instance: > set_attribute -instance .work.u2 -name block_ram -value FALSE
Forcing a Clock Buffer on an internal net: > set_attribute -net sensor2_int -name PAD -value BUFGP
Some Xilinx-specific optimization variables and their default values are listed below. To change a variable, use the "set" command (for example, "set lut_max_fanout 6"). These variables will affect the entire design during optimization.
virtex_infer_gsr = FALSE (Enables GSR processing for the Xilinx Virtex family)
virtex_map_iob_registers = FALSE (Maps to IOB registers for Virtex)
virtex_map_srl = TRUE (Maps to SRL cells)
virtex_map_srl_pack = TRUE (Packs SRL cells into a single slice)
virtex_map_wide_clusters = TRUE (Maps to Wide clusters for Virtex)
map_muxcy = TRUE (Maps to MUXCY for Xilinx Virtex/Virtex-E)
lut_max_fanout = 15 (Specifies the net's fanout for LUT technologies [xilinx])
write_clb_packing = FALSE (Prints CLB packing [HBLKNM] info in XNF/EDIF, if available)
virtex_map_iob_registers = FALSE (Maps to IOB registers for Virtex)
bubble_tristates = FALSE (During optimization, it automatically bubbles 3-states to a level of hierarchy wherein all drivers become visible, or to a top-level if the boundary is 3-state)
For an HDL example of how to insert Xilinx attributes inside HDL, please refer to (Xilinx Solution 8074).