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AR# 9032

4.2i Foundation Simulator - Simulation Printouts: Clock signals appear duty-cycle distorted on the printout

Description

Keywords: print, simulation, foundation, duty-cycle, distorted

Urgency: Standard

General Description:
Clock signals (or other regular signals) are distorted when I print them from the Foundation Simulator. These signals appear correctly in the waveform view (on screen) of the simulator.

However, when they are printed, the signals seem to have the wrong duty-cycle (although positive edges appear to line up correctly on a number of signals).

解决方案

To work around this problem, increase the number of pages that are printed. This will decrease the scaling effect of the printout.
AR# 9032
创建日期 04/12/2000
Last Updated 08/12/2003
状态 Archive
Type 综合文章