Virtex and Spartan-II
On these devices, all I/O standards have an intrinsic diode between the I/O pad and ground that limits undershoot to greater than -1 V. The LVCMOS 2.5V, LVTTL, and PCI 5V standards are all 5V-tolerant (both inputs and outputs) and do not have a pull-up clamp enabled. Because configuration pins default to LVTTL, these only have pull-down clamp diodes enabled.
Virtex-E and Spartan-IIE
These devices are provided with a pull-up clamp diode between the I/O pad and VCCO that allows them to be 5V-tolerant and reduces overshoot. The clamp diode is available with all I/O standards (including all configuration pins), excluding LVDS, LVPECL, GTL, GTL+, or LVCMOS1.8/2.5.
Virtex-II Pro Only
For Virtex-II Pro devices, all JTAG pins do not have clamp diodes, and the TDO is open drain. For more information, see the Virtex-II Pro/Virtex-II Pro X 3.3V I/O Design Guidelines Application Note(XAPP659).
Virtex-II/-II Pro/-4/-5/-6 and Spartan-3
For these devices, the following pins have pull-up and pull-down clamp diodes:
Note: VCCINT, VCCO, GND have a protection circuit, however,it might not be an explicit diode to Vcco and GND.
Spartan -3A/-3AN/-6
These devices have no pull-up diode clamps and use a floating n-well instead. For more information, see the Virtex-II Pro/Virtex-II Pro X 3.3V I/O Design Guidelines Application Note(XAPP659).
| Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
|---|---|---|---|
| 51834 | SelectIO Design Assistant - Reliability and over driving IOs. | N/A | N/A |