UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 9065

3.1i Foundation ISE: Project Navigator requires top-level entity name to be placed last in file

Description

Keywords: VHDL, entity, hierarchical, multiple entities

Urgency: Standard

General Description:
In a hierarchical VHDL design where there are multiple entities per
file, Project Navigator might choose the wrong entity as the top level.
Currently, Project Navigator, picks the last entity in the file as the
top-level module. This can result in incorrect synthesis results.

解决方案

In order to avoid synthesis issues, users must place the top-level
entity last in the file.
AR# 9065
创建日期 04/17/2000
Last Updated 01/16/2003
状态 Archive
Type 综合文章