General Description: When running a design through the tools, BitGen displays the following error:
"ERROR:DesignRules:368 - Netcheck: Sourceless. Net $3I2/..... has no source"
Upon further inspection, it is found that this signal is an address line to a Virtex block RAM; there are no connections to this address line from anywhere in the device, but it has still been assigned a net name. Looking in the MAP report will confirm that this signal is indeed flagged as being sourceless.
This error occurs when all the block RAM WEA, ENA, RSTA, WEB, ENB, and RSTB control lines are driven by constants and some address lines are driven by the same constants. MAP ends up leaving undriven signal stubs on the address lines instead of tying them off to GLOBAL_LOGIC1/0. These undriven signal stubs on the block RAMs occur somewhat unpredictably, as they depend upon the order in which the block RAM constants are processed during the packing phase.