General Description: The coregen.log file produced when CORE Generator is invoked from a Foundation HDL project seems to display incorrect values for the XilinxFamily and DesignFlow variables. (This is only observed in the coregen.log report file, and not in the ".xco" file generated for the core, as the XCO file settings will be correct.)
This problem occurs when I:
1. Start Foundation and choose a new HDL project. 2. Launch CORE Generator from Foundation. (Tools->Design Entry-> CORE Generator) 3. Select Project->Project Options in COREGen, choose Verilog or VHDL for design entry, and select a family other than Spartan. 4. Generate the core and return to Foundation. 5. Select the Report Browser tab, and view the CORE Generator report.
In the coregen.log report, I see the following:
SET XilinxFamily = SPARTAN SET DesignFlow = Schematic
The commands recorded in the coregen.log file that set the XilinxFamily setting to "Spartan" and the DesignFlow to "Schematic" are executed when the CORE Generator reads in the default coregen.ini file that Foundation places in every new project. This behavior is seen only when you invoke CORE Generator directly from Project Manager (because you are not prompted for a target architecture immediately after creating a Foundation HDL project).
To work around this problem, invoke CORE Generator from Foundation HDL Editor instead of from Project Manager.
With either method, the correct settings are recorded in the core's XCO file.