AR# 9098


3.1i COREGEN - Presence of HU_SET attributes may cause RLOC'ing of CORE Generator modules to fail


Keywords: rpm, rloc, constraint, accumulator, multiplier, 4K, PDA, FIR filter

Urgency: Hot

General Description:
Some CORE Generator modules use HU_SET attributes to define RPM subblocks of
related logic when constructing the module. One common application is to use the
HU_SET attributes to define separate carry chains within a core.

An unfortunate side effect of the presence of this attribute is that it prevents you from
applying RLOCs to the top level of the module to build more larger, more complex
RPMs from these CORE Generator modules.

The following cores are known to have this difficulty:
VP mult v1.0
twos_comp v1.0
twos_comp v2.0
Sin Cos LUT v1.0 (but NO HU_SETs in v2.0)
async FIFO v1.0
async fifo v2.0



If the particular Coregen module you are trying to RLOC contains
HU_SET attributes (you will usually see two or more of these),
instead of RLOC'ing the main core, you can RLOC the sub-modules
individually by specifying RLOC constraints for the component
subblocks in a UCF file.


Another workaround is to simply remove all the HU_SET attribues from the edif
file of the core. Then apply the RLOC constraint to the main Coregen module.
The constraint can be applied through a UCF file or by using the Xilinx Floorplanner

Note that the impact of removing the HU_SET attributes may reduce the performance
because the subhierarchy defined by the HU_SET attributes will no
longer exist.


This problem is scheduled to be fixed in next IP update (D_ip2) scheduled
for November 2000.
AR# 9098
日期 08/23/2002
状态 Archive
Type 综合文章
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