AR# 9149


ModelSim (MXE, SE, PE) - "ERROR: "Too many port connections - fatal error" (VHDL, Verilog)


General Description:

I am compiling a VHDL or Verilog design in ModelSim and encounter the following error message:

"Too many port connections - fatal error."


Ensure that there are no unused signals declared in the port list.

ModelSim gives this error if the number of connections in the port mapping are different than those in the module/entity being instantiated.

AR# 9149
日期 12/15/2012
状态 Active
Type 综合文章
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