General Description: When a schematic is selected as the source file, one of the Processes available under Design Entry Utilities is called View VHDL or Verilog Functional Model. This process generates the VHDL or Verilog netlist for the selected schematic.
Once this process is run and the file is created, running the process again will not regenerate the netlist, even if the schematic source is out of date. It simply opens the existing netlist.
There are several ways to regenerate the netlist:
1- Run Synthesis. 2- Use the Re-Run All option. 3- Delete the existing netlist. 4- Run any Implementation process.