Description: When performing timing simulation on a Virtex design witch contains Block Ram, Logic simulator may give a warning similar to the following:
Signal: My_Mem/BU0/INTERNAL_BLOCKRAM.GSR - too short PULSE, missing time 11.4ns
The warning occurs no matter how long the GSR pin is held high.
The 'too short PULSE' warning is incorrect - it is an error in the Foundation simulation model.
A user should be able to safely ignore this warning as long as they verify that the GSR pin has been held high longer than the minimum GSR pulse width specification in the Data Book (typically less than 15 nS).
To avoid this warning a user may edit the time_sim.edn file. 1) Search for all instances of the PWGSRHI property statement. Example: (property PWGSRHI (integer 13000)(unit TIME) (owner "Xilinx")) 2)Either delete the entire line or change the integer value to a small number like 100.
This error will be fixed for the Foundation 3.1 release